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You're at: ... > PCI to USB/Firewire > PCI to Firewire IEEE1394b > IEEE 1394a FireWire PCI Card with Internal 9-pin Header, VIA Chipset
  Multi-IO Connectivity
  PCI to Firewire IEEE1394a
IEEE 1394a FireWire PCI Card with Internal 9-pin Header, VIA Chipset (SD-VIA-FW1E1H)
  • IEEE 1394a FireWire PCI Card with Internal 9-pin Header, VIA Chipset

  • Firewire 1394a port: 1 x IEEE1394.A External Ports + 1 x IEEE1394.A Internal Header



  • VIA 6307 PCI to FireWire IEEE1394.a controller chip
  • Type : IEEE1394.A compliant OHCI specification V0.94
  • Port : 1 x IEEE1394.A External Ports + 1 x IEEE1394.A Internal Header
  • Speed : Transfer data rates of 100, 200 and 400Mbits/sec.
  • Interrupter : Plug and play Bus : PCI Bus
  • Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus and the P1394a Supplement 2.0.
  • Full P1394a Supplement Support includes: * Arbitrated short reset, * Connection Debounce, * Multispeed Concatenation, * Ack Accelerated Arbitration, * Fly-By Concatenation, * Programmable Port Disable, Suspend, Resume, * PHY IDs Do Not Increment Past 63
  • Provides Two 1394a Fully Compliant Cable Ports at 100/200/400 Megabits per Second (Mbit/s)
  • Logic Performs Bus Initialization and Arbitration Functions
  • Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding
  • Incoming Data Resynchronized to Local Clock.
  • Data Interface to Link-Layer Controller Provided Through 2/4/8 Parallel Lines at 49.152 MHz
  • 24.576 MHZ Crystal Oscillator and PLL Provide TX/RX Data at 100/200/400 Mbps and Link-Layer Controller Clock at 49.152 MHZ.
  • Cable Power Presence Monitoring.
  • Programmable Node Power Class Information for System Power Management
  • Embedded Bus Holder Isolation to Link Layer Controller Interface
  • Optional On-chip Resistors to Reduce Component Counts for Electrical Isolation to Link Layer Controller Interface
  • Fully Compliant P1394a 2.0 PHY Map
  • Separate TPBIAS for Each Port
  • Fully Interoperable with IEEE Std1394-1995 Devices
  • Cable Ports Monitor Line Conditions for Active Connection to Remote Node
  • Low Power Design for Battery-Powered Applications includes: User Controlled Power-Down via PD, Automatic Device Power-Down during All Ports Suspended and Link Interface Disabled, Link Interface Power-Down via Inactive LPS, Automatic Inactive Ports Powered-Down, and Automatic Inactive Logic Power-Down
  • Self Power Up Reset and Pinless PLL to Reduce Component Counts on System
  • Supports Windows 98SE/ME/2000/XP, MAC OS 9.0 & above.


System Requirement
  • PC computer with PCI Slot
  • MS Windows 98/98SE/ME/2000/XP

  • PCI FireWire Card
  • User's manual

Part number
Chip set
VIA 6307

Related Link

PCI 32-bit Firewire 1394b Controller Card

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